1. (Field of the Invention)
The present invention relates to a semiconductor memory device having a plurality of memory cells of one transistor - one capacitor type, and more particularly, to the memory cell which has an improved capacitor structure.
2. (Description of Related Art)
A semiconductor memory cell, particularly, a memory cell of the type consisting of one transistor and one capacitor, adapted to; stores binary information in the form of electric charge has a small cell area and is therefore suited for a large capacity memory cell, of a high integration density. However as the memory cell size has become smaller with a higher integration density of a memory cell, the capacitor area in the cell structure has become smaller too. The decrease in the storage charge due to the decrease in the capacitor area invites a problem in immunity against .alpha. particles and causes a deterioration in sensitivity of a sense amplifier.
Technologies for forming a large storage capacitance irrespective of the decrease in the memory cell area have heretofore been proposed in order to solve the problems described above. For example, the article entitled "NOVEL HIGH DENSITY, STACKED CAPACITOR MOSRAM" by M. Koyanagi et al. and published in the Proceedings of the International Electron Devices Meeting, 1978, pp. 348-351 discloses a structure wherein the storage capacitor includes two layers of polycrystalline. The first silicon layer is electrically connected to the source electrode of a switching transistor and the second layer is kept at a predetermined potential as the opposite electrode of the first layer. The of charge stored in this memory cell is determined by the area of the first and second layers and they are stacked together on the switching transistor of the same memory cell. Therefore, the capacitance and accordingly the charge can be enhanced to some extent.
However, the conventional structure proposed in the papers cannot have a sufficient capacitance when the memory cell area is further reduced permitting higher integration of the memory cells, because its capacitor-forming polycrystalline silicon layers are formed only on one switching transistor belonging to the same memory cell and only on a portion of a field insulating layer near the switching transistor.